The present invention relates generally to clocking circuitry for digital systems, and, more particularly, to a high frequency state machine divider having low power consumption.
In modern digital circuits and systems, such as digital signal processors for example, it is often advantageous to generate multiple clock signals of various frequencies from a smaller set of reference frequencies. Additionally, these applications may also call for each generated frequency to have no common factors with the other generated clock frequencies (i.e., the ratio of each generated frequency to the reference frequency might not share any prime factors with other generated frequencies). In many cases, it is also desirable that the generated frequencies be software or firmware controlled to accommodate different applications.
To date, many solutions exist that employ numerous analog circuits, such as voltage-controlled oscillators (VCO) and phase-locked loops (PLL). However, these circuits are costly to implement due to their relatively large size, power requirements, and sensitivity to electrical as well as physical design rules. In addition to these cumbersome and costly analog circuits, several current approaches allow for the generation of multiple clock frequencies using a single clock frequency as the input clock for multiple clock-dividers. In several of these systems, a clock divider may be easily constructed to divide a reference frequency by powers of two (i.e., 2n) or by integer values. However, the complexity of the system increases when the divisor is not a power of two, or even a non-integer value.
Digital division circuits, on the other hand, are often limited to division by even integers. Some digital dividers (which are capable of odd division) generate a clock signal that varies from a fifty percent duty cycle by one half of a clock cycle because odd division with a fifty percent duty cycle requires alternately aligning the generated clock to the rising and falling edges of the input clock. Other existing digital dividers capable of odd division that generate clock signals accurate to the proper half cycle may still compromise their duty cycle symmetry by using different clock signals to generate rising and falling edges or by using uneven numbers of gates in the logical paths which generate the rising and falling edges of the output clock.
Moreover, with the use of a conventional shift register technique for dividing an input clock signal, there are numerous latching elements (and therefore individual switching transistors) associated therewith, which increases overall current usage and power consumption. Given the continued reduced scaling of integrated circuit devices, it therefore is desirable to be able to implement a digital frequency divider architecture that may be used at high frequencies, but that consumes less power than conventional approaches.